ALTERA TERASIC USB BLASTER DRIVER

For this investigation, it doesn’t matter what gets transported when, but it’s almost certain that the slow clock cycles are used to move the JTAG TAP from iDLE state to the scan DR or scan IR state, and that the fast clock groups are used to rapidly scan data in and out of a scan data register. In the middle there are 16 groups with fast clock cycles each group is itself 8 clock cycles. The Terasic doesn’t have that problem: Yes, delete it Cancel. Sign up Already a member? In addition, there are roughly 3 idle cycles between a fast clock group. This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command.

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Terasic vs Cheap Clone USB Blaster

We have a prefix with 8 slow clocks, but in between the second and the third slow clock, there’s a signal fast clock group. We see a similar pattern, but interestingly enough, it’s not the same. And at the end you have a suffix with 2 slow clock cycles.

It looks like the cheap clone is able to squeeze out bits really fast, but there’s quite a bit of software overhead in processing the next byte in the USB packet. When you zoom in on the slow clock cycles, you can measure a TCK frequency of kHz: The cheap clone was never able to get blaater contact. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today: The set of signals below that is a slightly zoomed in terasix of the one above.

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It’s not that it’s broken: What remains is the question about why the cheap clone doesn’t work. A fast clock group sets the clock at 12MHz instead of 6MHz. In addition, there are roughly 3 idle cycles between a fast clock group. For the cheap clone, the spacing is huge: Sign up Already a member? As I wrote earlierthe biggest issue with the cheap clone is that it doesn’t work on my eeColor Color3 board.

The most important signal here is TCK, in yellow. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today:. All processing is done with a simply state machine.

:: Terasic Inc. – Expertise in FPGA/ASIC Design ::

And here’s the equivalent of the cheap clone. Meanwhile, during a fast clock group, the clock toggles at 6MHz. The suffix is really different, with 6 clock clocks but also a fast clock group in between. The Terasic doesn’t have that problem: But the cheap clone runs TCK at exactly double the speed of the Terasic, and both devices only use a flimsy, cheap flat cable. While the Terasic was rock solid in its communication with the Color3 board. For the overview, look at the upper set.

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It may be that 12MHz is really just pushing things too much. If we ignore for a second that the cheap clone doesn’t work on this particular board, the biggest consequence of the chapeau clone is that bulk transfers are much teeasic A really interesting difference is in the spacing between fast wltera groups: In the middle there are 16 groups with fast clock cycles each group is itself 8 blasetr cycles.

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Terasic – USB Blaster Cable

tedasic This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command. For this investigation, it doesn’t matter what gets transported when, but it’s almost certain that the slow clock cycles are used to move the JTAG TAP from iDLE state to the scan DR or scan IR state, and that the fast clock groups are used to rapidly scan data in and out of a scan data register.

In the middle we have the expected 16 fast clock groups. My money is on blaxter clock speed: There are 3 major sections: Zooming in on the slow clocks, we see a clock frequency of kHz.